1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacture thereof, and in particular, to a semiconductor device having a seal ring provided so as to surround the periphery of a semiconductor integrated circuit, and a method of manufacture thereof.
2. Description of the Background Art
In a manufacturing process for a semiconductor device, a semiconductor substrate is cut along dicing line portions, and thereby, is separated into individual LSI chips after a plurality of semiconductor elements have been formed on the semiconductor substrate. At this time, multiple interlayer insulating films layered during the process for forming the semiconductor elements are exposed from the cut section of the dicing line portions.
These interlayer insulating films and interfaces between the interlayer insulating films become paths for moisture to penetrate, and there is a possibility that these may become a problem in terms of reliability in such a manner that these may cause a malfunction of the semiconductor device.
In addition, cracking may occur in the interlayer insulating films due to stress at the time of dicing or stress caused by a difference in the coefficient of thermal expansion between the interlayer insulating films and the molding resin that is used at the time of the packaging of the LSI chip, and this cracking may become a path for moisture to penetrate.
As a measure for these, a configuration is adopted where a structure in loop form, which is referred to as a seal ring or a guard ring, is provided so as to surround the periphery of a region where a semiconductor integrated circuit is formed.
The seal ring is formed in the process for forming wiring layers or contact portions, which are formed in the region where the semiconductor integrated circuit is formed, and the same material for the wiring layers and the contact portions is used.
FIG. 17 is a cross sectional diagram showing the configuration of a seal ring according to a background technology of this invention. As shown in FIG. 17, a seal ring 90 is provided between the region where a circuit is formed on a semiconductor substrate 1 and the dicing region.
FIG. 17 shows, as an example of a semiconductor element that is provided on the semiconductor substrate 1, such as a silicon substrate, a configuration where a MOS transistor Q1 is provided in an active region defined by an isolation insulating film 2.
The MOS transistor Q1 is formed so as to have a gate electrode 32 provided on the semiconductor substrate 1 with a gate insulating film 31 in between, side wall insulating films 33 provided on the sides of the gate electrode 32, and source/drain layers 34 provided in the surface of the semiconductor substrate 1 on both sides and outside of the gate electrode 32 in the direction of the gate length.
Additionally, an interlayer insulating film 4 is provided on the semiconductor substrate 1 so as to cover the MOS transistor Q1, and on top of that, interlayer insulating films 5, 6, 7, 8, 9, 10 and 11 are sequentially provided so as to form a multilayer structure. Here, etching stopper films ES are provided between the respective interlayer insulating films.
Additionally, wiring layers and contact portions which are electrically connected to the MOS transistor Q1 are provided to these interlayer insulating films 4 to 11 in the region where the circuit is formed so as to form multilevel wiring layers.
That is to say, two contact portions 4a are provided so as to penetrate the interlayer insulating film 4 and reach the source/drain layers 34.
In addition, a plurality of wiring layers 5a are provided so as to penetrate the interlayer insulating film 5 and the etching stopper film ES on top of the interlayer insulating film 4. Two out of the plurality of wiring layers 5a are formed so as to be connected to the two contact portions 4a provided in the interlayer insulating film 4.
In addition, a plurality of contact portions 6a are provided so as to penetrate the interlayer insulating film 6 and the etching stopper film ES on top of the interlayer insulating film 5, and two of the plurality of contact portions 6a are formed so as to be connected to the wiring layers 5a, which are electrically connected to the source/drain layers 34 of the MOS transistor Q1.
Additionally, one of the plurality of contact portions 6a, which is electrically connected to one of the source/drain layers 34 of the MOS transistor Q1, is connected to a wiring layer 7a, which is provided in the interlayer insulating film 6. The wiring layer 7a is provided on top of one of the contact portions 6a, and the wiring layer 7a and the contact portion 6a are formed in accordance with a dual damascene method.
In addition, two contact portions 8a are provided so as to penetrate the interlayer insulating film 7 and the etching stopper film ES on top of the interlayer insulating film 6, and one contact portion 8a is formed so as to be connected to the contact portion 6a, which is electrically connected to the source/drain layer 34 of the MOS transistor Q1.
Additionally, the two contact portions 8a are connected to wiring layers 9a, which are provided in the interlayer insulating film 7. The wiring layers 9a are provided on top of the contact portions 8a and the wiring layers 9a, and the contact portions 8a are formed in accordance with a dual damascene method.
In addition, a contact portion 10a is provided so as to penetrate the interlayer insulating film 8 and the etching stopper film ES on top of the interlayer insulating film 7, and this contact portion 10a is formed so as to be connected to the wiring layer 9a, which is electrically connected to the source/drain layer 34 of the MOS transistor Q1.
Additionally, the contact portion 10a is connected to a wiring layer 11a, which is provided in the interlayer insulating film 8. The wiring layer 11a is provided on top of the contact portion 10a, and the wiring layer 11a and the contact portion 10a are formed in accordance with a dual damascene method.
In addition, a contact portion 12a is provided so as to penetrate the interlayer insulating film 9 and the etching stopper film ES on top of the interlayer insulating film 8, and this contact portion 12a is formed so as to be connected to the wiring layer 11a, which is electrically connected to the source/drain layer 34 of the MOS transistor Q1.
Additionally, the contact portion 12a is connected to a wiring layer 13a, which is provided in the interlayer insulating film 9. The wiring layer 13a is provided on top of the contact portion 12a, and the wiring layer 13a and the contact portion 12a are formed in accordance with a dual damascene method.
In addition, a contact portion 14a is provided so as to penetrate the interlayer insulating film 10 and the etching stopper film ES on top of the interlayer insulating film 9, and this contact portion 14a is formed so as to be connected to the wiring layer 13a, which is electrically connected to the source/drain layer 34 of the MOS transistor Q1.
Additionally, the contact portion 14a is connected to a wiring layer 15a, which is provided in the interlayer insulating film 10. The wiring layer 15a is provided on top of the contact portion 14a, and the wiring layer 15a and the contact portion 14a are formed in accordance with a dual damascene method.
Here, barrier metal layers BM1 are provided between the above described contact portions and the interlayer insulating films, as well as between the above described wiring layers and the interlayer insulating films, and thus, the material that forms the contact portions and the wiring layers does not make direct contact with the interlayer insulating films in the configuration.
In addition, a passivation film 19 is provided on top of the interlayer insulating film 11, and a polyimide film 20 is provided on top of the passivation film 19.
The seal ring 90 is formed in the process for forming the above described contact portions and wiring layers, which are formed between the respective interlayer insulating films.
That is to say, a sealing layer 4b is formed in the interlayer insulating film 4 during the process for forming contact portions 4a; a sealing layer 5b is formed in the interlayer insulating film 5 during the process for forming wiring layers 5a; sealing layers 6b and 7b are formed in the interlayer insulating film 6 during the dual damascene process for a contact portion 6a and a wiring layer 7a, respectively; sealing layers 8b and 9b are formed in the interlayer insulating film 7 during the dual damascene process for a contact portion 8a and a wiring layer 9a, respectively; sealing layers 10b and 11b are formed in the interlayer insulating film 8 during the dual damascene process for a contact portion 10a and a wiring layer 11a, respectively; sealing layers 12b and 13b are formed in the interlayer insulating film 9 during the dual damascene process for a contact portion 12a and a wiring layer 13a, respectively and sealing layers 14b and 15b are formed in the interlayer insulating film 10 during the dual damascene process for a contact portion 14a and a wiring layer 15a, respectively.
Here, the width of the sealing layers 4b, 6b, 8b, 10b, 12b and 14b is narrower than the width of the sealing layers 5b, 7b, 9b, 11b, 13b and 15b respectively formed thereon, and therefore, the cross sectional form of the respective combinations of the sealing layers 4b and 5b, the sealing layers 6b and 7b, the sealing layers 8b and 9b, the sealing layers 10b and 11b, the sealing layers 12b and 13b, as well as the ceiling layers 14b and 15b, is in T-shape.
In addition, a sealing layer 16b is provided so as to penetrate the interlayer insulating film 11 and the etching stopper film ES on top of the interlayer insulating film 10 and reach the sealing layer 15b, and a sealing layer 17b is provided on the interlayer insulating film 11 so as to cover the top portion of the sealing layer 16b. 
The sealing layer 17b is formed during the process for forming a wiring layer (not shown), which is the top layer in the region where the circuit is formed, and is formed of, for example, aluminum (Al).
In addition, the sealing layer 16b is formed during the process for forming a contact portion (not shown) for electrically connecting the wiring layer, which is the top layer in the region where the circuit is formed, to the wiring layer 15, and a barrier metal layer BM2 is provided between the sealing layer 16b and the interlayer insulating film.
Here, the sealing layers 4b to 17b are provided so as to be sequentially layered, and the seal ring 90 functions as a barrier against the moisture that has penetrated from the cut section of the exposed interlayer insulating films 4 to 11, and against the spreading of the cracks that have been created due to stress.
In addition, as for the configuration other than that of the above described seal ring 90, Japanese Patent Application Laid-Open No. 2000-277465, for example, discloses a configuration where seal rings are provided in a double structure in such a manner that the outer seal ring, which is close to the dicing portion, has a configuration where conductive layers having the same width are layered from the top layer to the bottom layer, and the inner seal ring is formed in the process for forming the wiring layers and the contact portions.
In addition, Japanese Patent Application Laid-Open No. 2004-296904 discloses a seal ring where conductive layers having the same width are layered from the top layer to the bottom layer in the vicinity of the dicing portion.
In recent years, miniaturization of the structure, increase in the integration and increase in the speed of operation of semiconductor devices have been progressing, and together with these, the importance of reduction in the resistance of wires has been increasing, and copper (Cu) having a relatively low resistance has been used as a wire material.
In the case where Cu is used as the wire material, it is general to form wiring layers and contact portions using a dual damascene method, and as described in reference to FIG. 17, the sealing layers 6b to 15b, from among the sealing layers 4b to 15b that form the seal ring 90, are formed using a dual damascene method.
Here, according to the dual damascene method, holes, which later become contact portions, are created so as to penetrate the interlayer insulating film, and after that, these holes are filled in once with a resin material, and in this state, trenches, which become wiring layers, are created through etching. This is done in order to prevent the already formed wiring layers in the lower layer from being etched.
However, the volume of the sealing layers 6b to 15b, which form the seal ring 90, is large in comparison with the volume of the corresponding contact portions and wiring layers. This is because the sealing layers 6b to 15b are formed so as to surround the region where the circuit is formed.
In particular, the volume of the sealing layers, which are formed in the same process for the contact portions, is extremely large in comparison with the contact portions, and therefore, it is technically difficult to fill the trenches for the formation of these sealing layers with a resin material. In the case where etching is carried out in order to create trenches, which become wiring layers in a state where filling with the resin material is insufficient, there is a possibility that the already formed sealing layers in the lower layer may be partially removed through etching, and in such a case, voids are created between the sealing layers in the upper layer and the sealing layers in the lower layer, making the connection portions of the two fragile, and there is a possibility that the function of the seal ring may deteriorate.
In addition, in these days, the relative dielectric constant of the interlayer insulating films tends to be low, and the adhesiveness between the interlayer insulating films tends to be low together with the lowering of the relative dielectric constant. Here, the configuration of the seal ring 90 or the like, where sealing layers of which the cross sectional form is in T-shape are layered, has effects of preventing the interlayer insulating films from peeling off from each other, though in the case where a seal ring having a structure where conductive layers having the same width are layered from the top layer to the bottom layer is adopted as disclosed in Japanese Patent Application Laid-Open No. 2004-296904, there is a possibility that the above described effects may be reduced.
The present invention is provided in order to solve the above described problems, and an object of the invention is to provide a semiconductor device where the structure of a seal ring is optimized so that a seal ring, which secures the function of a barrier against the penetration of moisture from the cut section along the dicing portion and the spreading of cracks, is provided, as well as a manufacturing method for the same.